EE3300/EE5300 Electronics Applications

Week 2 Tutorial

Workshop discussion question

AoE Figure 5.1 (p. 294) shows a design for a precision voltage meter.

Discussion questions:

• Suppose that nothing is connected to the meter ( open circuit). If the op-amp is the “cheap and cheerful” LF411, what is the worst case error in the meter reading due to:
  • the input offset voltage?
  • the input bias current?
• What is the required specification for the op-amp in terms of input offset voltage and input bias current to ensure that the meter error is less than 1% of the full scale reading?

Tutorial questions

Frequency response analysis questions

1. In the lecture notes, we considered the case of a Zener diode being used as a voltage reference (Figure 1a). In the notes, we found that an unreasonably large capacitor was required for the specific case that was analysed. Suppose now that you need to refine that design but you are limited to a 100 μF capacitor.

   The given values are and

   Sketch the magnitude Bode plot of the two circuits (a) and (b) in Figure 1 and illustrate the suitability of this transfer function to attenuate 100 Hz noise. (Solution)

Razavi Chapter 11 problems (JCU login required)

1. Razavi Exercise 11.1. (Solution)

2. Razavi Exercise 11.2. (Solution)

3. Razavi Exercise 11.3. (Solution)

4. Razavi Exercise 11.6. (Solution)

5. Razavi Exercise 11.9. (Solution)

6. Razavi Exercise 11.16. (Solution)

7. Razavi Exercise 11.22. (Solution)

Frequency response design questions

1. Razavi Exercise 11.55. (Solution)

2. Razavi Exercise 11.57. (Solution)

Feedback questions

Razavi Chapter 12 problems (JCU login required)

1. Razavi Exercise 12.4 and 12.5. (Solution)

2. Razavi Exercise 12.10. Note a correction to the question: the summing junction needs to be positive at both inputs because is already inverting. (Solution)

3. Razavi Exercise 12.25. (Solution)

4. Razavi Exercise 12.26. (Solution)

Design problem

1. Figure 2 uses current-controlled voltage feedback to regulate the current flowing in the load .

   The resistor represents a device that requires an accurately controlled current. We would like the design to support rapid changes in and , i.e. the regulator must have a high bandwidth.

   1. Confirm that the feedback is negative (and therefore the circuit will work as expected).

   2. Calculate the value of that will ensure 10 mA of current in the load. This calculation will set the large signal behaviour (i.e. DC operating point) of the circuit.

      Hint: Recall that in a negative feedback system, the returned feedback signal is a good replica of the input signal. Therefore is approximately equal to the voltage on .

   3. Treating as the input signal, construct a small signal model for the low-frequency, open-loop transfer function

      You may assume that the op-amp has a DC open-loop gain of .

      (Hint: consider the feedback path to be disconnected and put a ground at the op-amp’s non-inverting input.)

   4. Analyse the circuit to find the small signal loop gain.

   5. Using the results from parts (c) and (d), write down the small signal closed-loop transfer function at low frequencies.

   6. The IRLML5203 transistor is documented in its datasheet to have a forward transconductance (written as , equivalent to in our notation) of 3.1 S at . Use the formula to estimate for this transistor, and hence calculate for the actual operating condition of .

   7. The transistor has a documented rise time of 18 ns and fall time of 52 ns. The reciprocals of these numbers are 55 MHz and 19 MHz, respectively. Therefore as a rough estimate, we anticipate that the transistor is much faster than the op-amp, whose unity-gain bandwidth is a mere 1 MHz. Consequently, we will consider the frequency response of this circuit to be dominated by the op-amp. Since the LMV324A datasheet Figure 6-4 shows the open-loop gain decaying by -20 dB/decade, we can approximately model the op-amp with a simple one pole transfer function. The datasheet says that the DC open-loop gain is and the gain drops to 0 dB at 1 MHz. Therefore, estimate the pole frequency (and hence the open-loop bandwidth of the op-amp).

   8. The closed-loop bandwidth is enhanced from the open-loop bandwidth by a factor of ). Using your results from above, calculate the expected bandwidth of the overall circuit.

   9. Simulate the circuit and use an AC analysis to measure the bandwidth. You will need to set up to have a DC value based on your result from part (b) and a small AC magnitude in order to test the response. The variable that you want to plot is . Does your bandwidth compare to what you calculated in part (h)?

   Solution